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| Data Sheet SII3726 SATA Port Multiplier Data Sheet Document # SiI-DS-0121-C1 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Silicon Image, Inc. June, 2006 Silicon Image, Inc. reserves the right to make changes to the product(s) or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable, but Silicon Image, Inc. shall not be responsible for any errors that may appear in this document. Silicon Image, Inc. makes no commitment to update or keep current the information contained in this document. However, no responsibility is assumed for its use; or any infringement of patents or other rights of third parties, which may result from its use. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Silicon Image, Inc. products are not designed or intended for use in Life Support Systems. A Life Support System is a product or system intended to support or sustain life, which if it fails, can be reasonably expected to result in significant personal injury or death. If Buyer or any of its direct or indirect customers applies any product purchased or licensed from Silicon Image, Inc. to any such unauthorized use, Buyer shall indemnify and hold Silicon Image, Inc., its affiliates and their respective suppliers, harmless against all claims, costs, damages and expenses arising directly or indirectly, out of any such unintended or unauthorized use, even if such claims alleges that Silicon Image, Inc. or any other person or entity was negligent in designing or manufacturing the product. Specifications are subject to change without notice Copyright Notice Copyright (c) 2006 Silicon Image, Inc. All rights reserved. These materials contain proprietary and confidential information (including trade secrets, copyright and other interests) of Silicon Image, Inc. You may not use these materials except only for your bona fide non-commercial evaluation of your potential purchase of products and/services from Silicon Image or its affiliates, and/or only in connection with your purchase of products and/or services from Silicon Image or its affiliates, and only in accordance with the terms and conditions herein. You have no right to copy, modify, transfer, sublicense, publicly display, create derivative works of or distribute these materials, or otherwise make these materials available, in whole or in part, to any third party. Trademark Acknowledgment Silicon ImageTM, VastLaneTM, SteelVineTM, PinnaClearTM, SimplayTM, Simplay HDTM, SatalinkTM, and TMDSTM are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. HDMITM, the HDMI logo and High-Definition Multimedia InterfaceTM are trademarks or registered trademarks of, and are used under license from, HDMI Licensing, LLC. Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. Revision History Revision A B C 4/2005 6/2006 7/2006 Date Comment Derived from preliminary specification rev. 0.51 Updated green package, Converted to standard format Datasheet is no longer under NDA, removed confidential markings. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 2 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Table of Contents Table of Contents.......................................................................................................................................... 3 Table of Figures ............................................................................................................................................ 5 Table of Tables .............................................................................................................................................. 5 Overview ........................................................................................................................................................ 6 Description ................................................................................................................................................ 6 Features ..................................................................................................................................................... 6 Overall Features ...................................................................................................................................... 6 Robust, High Performance PHY Technology .......................................................................................... 6 Storage System Features........................................................................................................................ 6 Architecture Features .............................................................................................................................. 6 Applications ............................................................................................................................................. 7 Functional Block Diagram ........................................................................................................................... 7 SATA Ports ................................................................................................................................................. 8 LED Modes................................................................................................................................................. 8 Device/Host LED Modes ......................................................................................................................... 8 System LED Modes................................................................................................................................. 8 High Speed Serial Interface Optimization .............................................................................................. 9 PHY Configuration Settings..................................................................................................................... 9 Tx Eye Measurement .............................................................................................................................. 9 GPIO Support .......................................................................................................................................... 10 BIST Support ........................................................................................................................................... 10 Serial ATA Power Mode Request ........................................................................................................... 10 Device Enumeration Sequence ............................................................................................................. 10 Storage Enclosure Support ................................................................................................................... 11 Internal Register Space.............................................................................................................................. 12 General Status and Control (GSCR) Registers .................................................................................... 12 Port Status and Control Registers (PSCR) .............................................................................................. 17 Device Initialization .................................................................................................................................... 20 Auto-Initialization from the EEPROM.................................................................................................... 20 EEPROM Specifications........................................................................................................................ 20 EEPROM Read/Write Operations........................................................................................................... 20 System Reset........................................................................................................................................... 22 Electrical Characteristics........................................................................................................................... 23 Absolute Maximum Ratings................................................................................................................... 23 DC Specifications.................................................................................................................................... 23 SATA Interface DC Specifications ......................................................................................................... 24 CLKI SerDes Input Reference Clock Requirements ............................................................................ 25 SATA Interface Timing Specifications................................................................................................... 25 SATA Interface Transmitter Output Jitter Characteristics .................................................................. 26 Pin Descriptions ......................................................................................................................................... 27 SiI 3726 SATA Port Multiplier Pin-out.................................................................................................... 27 Package Pin Descriptions.......................................................................................................................... 37 Pin Descriptions...................................................................................................................................... 37 Package Information .................................................................................................................................. 38 Dimensions.............................................................................................................................................. 38 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 3 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Part Ordering Numbers: ........................................................................................................................ 39 References............................................................................................................................................... 40 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 4 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Table of Figures Figure 1: SiI 3726 SATA Port Multiplier Block Diagram .................................................................................. 7 Figure 2: Enclosure Management Support Overview................................................................................... 11 Figure 3: I2C Transfer Timing........................................................................................................................ 20 Figure 4: I2C Random Read and Write Timing ............................................................................................. 21 Figure 5: I2C Block Transfer.......................................................................................................................... 22 Figure 6: Power-Up Reset Circuit................................................................................................................. 22 Figure 7: Eye Diagram.................................................................................................................................. 24 Figure 8: Sil3726 Pinout Diagram................................................................................................................. 37 Figure 9: 364 Ball HSBGA Package Dimensions (in Millimeters) ................................................................ 38 Figure 10: Marking Specification - SII3726CB.............................................................................................. 39 Figure 11: Marking Specification - SII3726CBHU......................................................................................... 39 Table of Tables Table 1: Device or Host LED Modes and Descriptions................................................................................... 8 Table 2: System LED Modes and Descriptions .............................................................................................. 8 Table 3: PHY Configuration Settings .............................................................................................................. 9 Table 4: SError Bit Definitions....................................................................................................................... 18 Table 5: Absolute Maximum Ratings ............................................................................................................ 23 Table 6: DC Specifications............................................................................................................................ 23 Table 7: SATA Interface DC Specifications ................................................................................................... 24 Table 8: CLK1 SerDes Reference Clock Input Requirements...................................................................... 25 Table 9: SATA Interface Timing Specifications.............................................................................................. 25 Table 10: SATA Interface Transmitter Output Jitter Characteristics (1.5 G) ................................................. 26 Table 11: SATA Interface Transmitter Output Jitter Characteristics (3.0 G).................................................. 26 Table 12: SII3726 Pin List (Sorted by Pin Name) ......................................................................................... 27 Table 13: SII3726 Pin List (Sorted by Pin Number) ...................................................................................... 31 Table 14: Power Supply Pin List ................................................................................................................... 36 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 5 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Overview Description Silicon Images SiI 3726 SATA Port Multiplier is 1-to-5 SATA Port Multiplier designed to provide a high performance link between a single SATA host port and five SATA device ports. With its unique data aggregation capability and 3 Gbps serial link capability, the SiI 3726 SATA Port Multiplier is able to take full advantage of 3 Gbps host link bandwidth and FIS-based switching host controllers by bundling together data from device ports and sending it over the 3 Gbps host link. Additionally, the feature-rich SiI 3726 supports all the port multiplier related SATA II extensions allowing system designers to exploit the full potential of SATA in their storage solutions. The SiI 3726 SATA Port Multiplier supports host and device link rates of 1.5 Gbps and 3 Gbps with autonegotiation allowing system designers to utilize 3 Gbps host links with today's 1.5 Gbps hard drives, and to futureproof designs for the emergence of 3 Gbps SATA hard drives. Additionally, the SiI 3726 contains a SATA Enclosure Management Bridge (SEMB) to pass in-band enclosure management information between the host and an enclosure management device. Other important features include, programmable high drive capability for backplane and external applications, asynchronous notification to eliminate the need for host polling to determine if a device has been added or removed, and hot plug support. The SiI 3726 is designed for optimum power, performance and price. It is based on Silicon Images industry leading SATALink technology. It leverages much of the circuit innovation at the physical layer of Silicon Image's proprietary reduced-overhead Multi-layer Serial Link (MSLTM) architecture, which was pioneered and proven with our market-leading PanelLink(R) products. Silicon Image has shipped over 35 million units of PanelLink(R) products for host systems and displays in the PC and the CE markets, notable for their noisy operating conditions. Features Overall Features * * * * * * One-to-five native SATA Port Multiplier Full support for FIS-based switching and command-based switching SATA host controllers Advanced data aggregation architecture for ultra-fast read and write operations with FIS-based switching controllers 21mm x 21mm, 364 pin BGA package with a 20 x 20 array of balls High-speed, native SATA connections to host and device Host and device status and activity LEDs Robust, High Performance PHY Technology * * * * 1.5 Gbps and 3.0 Gbps PHY support with auto-negotiation Compliant with SATA II external PHY specifications Independently programmable PHY settings to support extended PCB trace lengths and external SATA applications Industry proven SATALink technology Storage System Features * * * * * Hot-plug and ATAPI support SATA Enclosure Management Bridge (SEMB) support with I2C interface to the external Storage Enclosure Processor (SEP) Far-end Re-timed loop-back BIST for host initiated system testing Supports host control of hard disk drive staggered spin-up Asynchronous notification support Architecture Features * * Features independent 8 kByte FIFO per device serial ATA channel for reads and writes High performance data movement between all SATA ports SiI-DS-0121-C1 6 (c) 2006 Silicon Image, Inc. SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Applications * * * Expansion Storage Bricks Disk Shelves Storage Enclosures Functional Block Diagram Figure 1 shows the Block Diagram for the SiI 3726 SATA Port Multiplier. Status LED Drivers BIST and JTAG Buffer SATA Device Port0 PLL Buffer SATA Device Port1 SATA Host Port Buffer Port Multiplier Buffer SATA Device Port2 Buffer SATA Enclosure Management Bridge Serial EEPROM Buffer SATA Device Port3 SATA Device Port4 Figure 1: SiI 3726 SATA Port Multiplier Block Diagram The following sections will describe the features of the port multiplier. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 7 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Ports The host port supports the SATA-II speed of 3 Gbps and auto-negotiates to 1.5 Gbps to interface with SATA-I host controllers. The device ports operate at SATA-II speeds of 3 Gbps or auto-negotiate to 1.5 Gbps. All ports support hot plug and extended (48 bit LBA) drive capability. LED Modes Device/Host LED Modes Table 1 shows the device or host LED modes and descriptions. The mode is determined by the LED_MODE pin (pin A3). LED pins are open-drain and sink current up to 12mA in their low voltage active state (LED On), or are high impedance in their high voltage non-active state (LED Off). These signals will operate with an external pullup resistor and LED. Each activity will turn on or off LED0 for approximately 70ms. The blinking rate is approximately 400ms on and 400ms off. Table 1: Device or Host LED Modes and Descriptions LED_MODE 0 (PC mode) 0 (PC mode) 0 (PC mode) 1 (Enterprise mode) 1 (Enterprise mode) LED1 Off On Blink Off On LED0 Off Off Blink Off Off Description Power on, no device attached PHY communication established, (activity = LED0 On) Error Power on, no device Error System LED Modes Table 2 shows the System LED modes and their descriptions. Table 2: System LED Modes and Descriptions Signal LED_S0 EEPROM load error On: Loading error Off: No loading errors System ready On: System is ready Off: System is not ready System error On: System error Off: No system errors Description LED_S1 LED_S2 In normal operation, if system reset is released, LED_S3 will turn-on while the firmware loads into the SiI 3726 SATA Port Multiplier (~ 1 second). When the firmware load is complete, LED_S1 will turn-on indicating the system is ready to be used. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 8 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. High Speed Serial Interface Optimization In order to accommodate different system environments, the port multiplier allows the designer to configure the device PHYs to support various cable/PCB lengths on each serial I/O independently. PHY Configuration Settings Table 3 shows the configuration settings and description for each high-speed serial port. Pre-emphasis and equalization are used to compensate the signal degradation due to increased cable lengths. Without pre-emphasis or equalization, jitter at the receiver end will increase along with the increase of the cable length, causing signal degradation and Bit Error Rate problems. The effect may depend on the system environment. Factors such as cable quality, PCB implementation, receiver load, etc. all affect the signal quality. Please consult with Silicon Image's technical support department for more information. Table 3: PHY Configuration Settings Serial Port Host Port Signal HIO[2:0] Settings and Description HIO[2:0] = 0b000 (Default). PC motherboard to device applications up to 1m internal cable, external desktop up to 2m external cable ((2 Meter eSATA cable) or short backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper) HIO[2:0] = 0b001: Tx amplitude will be 100mV lager than 000 setting HIO[2:0] = 0b010 - 0b100 (Reserved. please consult with Silicon Image technical support for this detail): external desktop up to 4m external cable or short backplane up to 30 inch of FR4 (0.012 mil trace width with 1 oz copper) 0b 010: Only pre-emphasis enabled 0b 011: Only equalization enabled 0b111: Both pre-emphasis and equalization enabled HIO[2:0] = 0b101 - 0b111 (Reserved. Contact Silicon Image Technical Support for details): external desktop longer than 4m external cable or short backplane longer than 30 inch of FR4 (0.012 mil trace width with 1 oz copper) 0b010: Only pre-emphasis enabled 0b011: Only equalization enabled 0b111: Both pre-emphasis and equalization enabled DxIO[1:0] = 0b00 (Default): PC motherboard to device applications up to 1m internal cable, external desktop up to 2m external cable (2 Meter eSATA cable) or short backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper) DxIO[1:0] = 0b01: Tx amplitude will be 100mV lager than 00 setting DxIO[1:0] = 0b10 (Reserved. Contact Silicon Image Technical Support): external desktop up to 4m external cable or short backplane up to 30 inch of FR4 (0.012 mil trace width with 1 oz copper). Both pre-emphasis and equalization are enabled DxIO[1:0] = 0b11 (Reserved. Contact Silicon Image Technical Support): external desktop longer than 4m external cable or short backplane longer than 30 inch of FR4 (0.012 mil trace width with 1 oz copper). Both pre-emphasis and equalization are enabled Device #0 Device #1 Device #2 Device #3 Device #4 DAIO[1:0] DBIO[1:0] DCIO[1:0] DDIO[1:0] DEIO[1:0] Tx Eye Measurement The SiI 3726 SATA Port Multiplier has the capability to output random (scrambled) and deterministic data patterns (primitives) to downstream devices bypassing the OOB sequence for eye measurement testing. Upon completing the device enumeration process, the port multiplier outputs COM_RESET/COMINIT periodically. This implementation maintains compatibility with the SATA compliant host/device and enables hot plug support. But this implementation also prevents evaluating the Tx eye quality by connecting it directly to the oscilloscope. By bypassing the OOB sequence after the host completes the device enumeration sequence, the Tx will output a random data pattern. The port multiplier can bypass the OOB sequence by setting pin Y12 (OOB_BP) to high. In addition to this, if CONT primitive is disabled by setting pin Y11 (CONT_DIS) to high, the Tx will output a deterministic data pattern. The output generation (1.5 G or 3.0 G) can be selected by pin W12 (TX_GEN). The random data pattern is a scrambled data pattern and useful for eye mask testing. The deterministic pattern is a repetitive pattern of primitives and is useful for jitter analysis. The primitive is normally synchronous and includes Align primitives every 256DWORDs. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 9 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. GPIO Support The 32 bits in General Status and Control Register [130] each correspond to its associated General Purpose Output pin on a write (GPO[31:0]). If the bit is set to 0, the GPO will output a high logic level. Bits [2:9] and [22:29] are not assigned to the pins and the value in the bit field does not effect the operation. The 32 bits in General Status and Control Register [130] each correspond to its associated General Purpose Input pin on a read (GPI[31:0]). If the GPI1 is high, bit 1 will be set. Some of these GPI pins are reserved for various other functions as follows. * * * Bit fields [12:10 / EMID [2:0] Bit fields [9:2] / 1000_0000b Bit fields [24:14] / DEIO[1], DDIO[0], DCIO[1:0], DBIO[1:0], DAIO[1:0] * Bits 27 and 25 / DEIO[0], DDIO[1] GPI pins have internal pull-downs, and GPO pins are initialized to drive low by the firmware. The Read/Write Port Multiplier command can be used to read or write the GSCR. Address 0x0F must be specified in PortNum field of the command FIS in order to read or write the GSCR. The details of the Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier Specification. BIST Support The SiI 3726 SATA Port Multiplier supports far-end retimed loopback BIST only as a target as described by the SATA II Port Multiplier Specification. If the port multiplier receives a BIST activated FIS, it enters BIST mode and loops back the SATA interface. The port multiplier does not propagate the BIST activated FIS to the other ports. Serial ATA Power Mode Request Either the host or the devices may initiate power mode requests. If the request is initiated by the device, upon receipt of the appropriate PMREQ (PMREQ_P or PMREQ_S) request, the port multiplier sends back the PMACK primitives and disables the TxP/TxN pair for the port. If the request is initiated by the host, the port multiplier sends back the PMACK primitives and disables the TxP/TxN pair for the host port. The port multiplier issues the PMREQ to the all attached devices. Upon receipt of PMACK primitives from the physical devices, the TxP/TxN pair will be disabled. Device Enumeration Sequence The device enumeration process is defined in the SATA II Port Multiplier Specification. Upon receipt of the software reset with 0x0F as the PM port number, the SiI 3726 SATA Port Multiplier issues a Register Frame Information Structure (FIS) with the Port Multiplier Signature. Before receiving the software reset with 0x0F as the PM port number, the port multiplier delivers all Frame Information Structures to port 0 regardless of the PM port number value in the receiving FIS. After sending the software reset with 0x0F as the PM port number, the PM aware host resets each device port by programming bit 1 in the SControl register and writing 0xFFFF_FFFF in the SError register to clear the bits in the register. The host should examine the SStatus and SError registers to determine whether or not a device is connected to the device ports. If a device is attached to the port, the host should initialize the device before it using it for a read or a write operation. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 10 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Storage Enclosure Support The SiI 3726 SATA Port Multiplier is compliant with the SATA II port multiplier specification. It has a SATA Enclosure Management Bridge (SEMB) that passes in-band enclosure management data between the host controller and a companion enclosure management device through an I2C bus. SATA HBA SII3726 SEMB I2C SEP Figure 2: Enclosure Management Support Overview The port multiplier supports the SAF-TE and SES protocols. The host issues Enclosure Management commands through the SATA interface. Enclosure Management commands use the SEP_ATTN commands in the Command register and the SEP command code in the Features register. The SEP command protocol is defined in the SAFTE or SES specification. The I2C interface is multi-master capable and can transfer data at 0 - 400 kbits/s. The SEMB I2C address is 0001xxx0, where xxx are selected using pins EM_ID[2:0]. This allows up to eight SiI 3726 SATA Port Multipliers on the same SEMB I2C bus. The SEP I2C address should be 0xC0, as defined in the SATA II specification. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 11 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Internal Register Space The SiI 3726 SATA Port Multiplier has 32-bit wide registers that control its internal operations. General Status and Control (GSCR) Registers These registers are defined in the SATA II Port Multiplier specification. The Read/Write Port Multiplier command is used to read or write the GSCR registers. Address 0x0F must be specified in the PortNum field of the command FIS in order to read or write the GSCR. The Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier Specification. Addr 0x00 GSCR[00] Name Product Identifier 31 23 15 7 Bit Label R/W 30 22 14 6 29 21 13 5 28 20 27 26 18 10 2 25 17 9 1 24 16 8 0 Default 0x3726 0x1095 Device ID 19 Device ID 12 11 Vendor ID 4 3 Vendor ID Description This register defines the Device ID and Vendor ID associated with the SiI 3726. 31:16 Device ID R The default value of 0x3726 identifies the device as Silicon Image SII3726. 15:0 Vendor ID R This field defaults to 0x1095 to identify the vendor as Silicon Image. Addr 0x01 GSCR[01] Name Revision Information 31 23 15 7 30 22 14 6 29 21 13 28 RSVD0 20 27 19 26 18 25 17 24 16 8 0 RSVD0 Default 0x0000 0x17 RSVD0 12 11 10 9 Revision ID/Chip Revision ID 5 4 3 2 1 RSVD0 PM spec Description Bit Label R/W This register defines the revision ID associated with the SII3726. 31:16 RSVD0 R This bit field is reserved and returns a zero value. 15:8 R Revision This bit field is set to indicate the revision level of the chip design, revision ID/Chip 0x17 is defined by this specification. Revision ID 7:3 RSVD0 R This bit field is reserved and returns a zero value. 2:1 PM spec R This register defines the Port Multiplier Specification Supports. This bit field is set to 0x11 to indicate that SiI 3726 supports the Port Multiplier Specification and 1.1. 0 RSVD0 R This bit field is reserved and returns a zero value. 0b00000 0b00 0b0 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 12 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x02 GSCR[02] Name Port Information 31 23 15 7 30 22 14 6 RSVD0 29 21 13 5 28 RSVD0 20 RSVD0 12 RSVD0 4 Description 27 19 11 3 26 18 10 25 17 9 24 16 8 0 Default 0x0000 000 0x6 2 1 Number of Fan-out ports Bit 31:4 3:0 Label RSVD0 Number of Fan-out ports R/W R R This register defines port information associated with the SII3726. This bit field is reserved and returns a zero value. This bit field is set to 0x06 to indicate that SII3726 supports one host and five device ports. Addr 0x20 GSCR[32] Name Error Information 31 23 15 30 22 14 29 21 13 5 Error Informat ion 28 27 26 18 10 2 Error Informat ion 25 17 9 1 Error Informat ion 24 16 8 0 Error Informat ion Default 0x0000 0b0 0b0 0b0 0b0 0b0 0b0 7 6 RSVDRW RSVDRW 20 19 RSVDRW 12 11 RSVDRW 4 3 Error Error Informat Informat ion ion Description Bit 31:06 5 4 3 2 1 0 Label RSVDRW Error Information Error Information Error Information Error Information Error Information Error Information R/W R/W R/W R/W R/W R/W R/W R/W This bit field is reserved and returns the value written to it. This bit is set to 1 when the bits in port5 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33].. This bit is set to 1 when the bits in port4 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port3 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port2 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port1 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. This bit is set to 1 when the bits in port0 PSCR[1] SError register are set. The bits used for this bit are selected by the GSCR[33]. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 13 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x21 GSCR[33] Name Error Information 31 23 15 7 30 22 14 6 29 21 13 5 28 27 26 18 10 2 25 17 9 1 24 16 8 0 Default 0x0400 FFFF Error Information 20 19 Error Information 12 11 Error Information 4 3 Error Information Description Bit 31:0 Label Error Information R/W R/W This bit field provides the bits used for error information in the GSCR[32] Error Information register. If the bit set to 1, that bit will be used by the GSCR[32]. Addr 0x40 GSCR[64] Name Optional Features Support 31 23 15 7 30 22 14 6 29 21 13 5 RSVD0 28 RSVD0 20 RSVD0 12 RSVD0 4 27 19 11 3 Async notificati on support 26 18 10 2 Dynami c SSC Transmi t Enable support 25 17 9 1 Issuing PMREQ _P to host support 24 16 8 0 BIST support Bit 31:4 3 Label RSVD0 Async notification support Dynamic SSC Transmit Enable support Issuing PMREQ_ P to host support BIST support R/W R R Description This bit field is reserved and returns a zero value. This bit field is set to 1 to indicate that the SII3726 supports Asynchronous notification. This bit field is set to 0 to indicate that the SII3726 does not support Dynamic SSC Transmit Enable. Default 0x0000 000 0b1 2 R 0b0 1 R This bit field is set to 0 to indicate that the SII3726 does not support issuing PMREQ_P to host. 0b0 0 R This bit field is set to 1 to indicate that the SII3726 supports BIST. 0b1 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 14 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x60 GSCR[96] Name Optional Features Enable 31 23 15 7 30 22 14 6 29 21 13 5 RSVD0 28 RSVD0 20 RSVD0 12 RSVD0 4 27 19 11 3 Enable Asynchr onous notificati on 26 18 10 2 Enable Dynamic SSC Transmit 25 17 9 1 Enable issuing PMREQ _P to host 24 16 8 0 Enable BIST Bit 31:4 3 Label RSVD0 Enable Asynchron ous notification Enable Dynamic SSC Transmit Enable issuing PMREQ_ P to host Enable BIST R/W R R Description This bit field is reserved and returns a zero value. Setting this bit enables Asynchronous notification. Default 0x0000 000 0b0 2 R The SII3726 does not support Dynamic SSC Transmit and setting this bit does not affect the operation. 0b0 1 R The SII3726 does not support issuing PMREQ_P to the host and setting this bit does not affect the operation. 0b0 0 R Setting this bit enables BIST. 0b1 Addr 0x03 - 0x1F GSCR[03-31], 0x22 - 0x3F GSCR[34-63], 0x41 - 0x5F GSCR[65-95], 0x61 - 0x7F GSCR[97-127] Bit 31:0 Label RSVD0 Name Reserved 31 23 15 7 30 22 14 6 29 21 13 5 28 RSVD0 20 RSVD0 12 RSVD0 4 RSVD0 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 R/W R Description This bit field is reserved and returns a zero value. Default 0x0000 0000 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 15 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x80 - 0x81 GSCR[128-129, 0x83 - 0xFF GSCR[131-255] Name Vendor Unique 31 23 15 7 30 22 14 6 29 21 13 5 28 27 26 18 10 2 25 17 9 1 24 16 8 0 Default 0x0000 0000 Vendor Unique 20 19 Vendor Unique 12 11 Vendor Unique 4 3 Vendor Unique Description Bit 31:0 Label Vendor Unique R/W R/W These registers define vendor unique and may be used by the firmware. The user shall not access these registers. Addr 0x82 GSCR[130] Name GPIO 31 23 15 7 30 22 14 6 29 21 13 5 28 GPIO 20 GPIO 12 GPIO 4 GPIO Description 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Default N/A Bit 31:0 Label GPIO R/W R/W The bit field is corresponding to the GPO pins on a write. If the bit 0 is set, the GPO 0 will output high. The bit field is corresponding to the GPI pins on a read. If the GPI 1 is high, the bit 1 will be set. GPI pins have internal pulldowns, and GPO pins will be initialized to drive low by the firmware. For details, see GPIO Support on page 10. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 16 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Port Status and Control Registers (PSCR) The registers are defined in the SATA II Extensions to Serial ATA 1.0a Specification. The Read/Write Port Multiplier command may be used to read or write the PSCR. The port number must be specified in the PortNum field of the command FIS in order to read or write the PSCR. The Read/Write Port Multiplier commands are defined in the SATA II Port Multiplier specification. Addr 0x00 PSCR[00] Name SStatus 23 15 7 Bit 31:12 11:08 Label RSVD0 IPM R/W R R 22 14 21 20 RSVD0 13 RSVD0 6 5 SPD 12 4 Description This bit field is reserved and returns a zero value. This field identifies the current interface power management state. 0000: Device not present or communicating not established 0001: Interface in active state 0010: Interface in partial power management state 0110: Interface in slumber power management state Others: Reserved This field identifies the negotiated interface communication speed. 0000: No negotiated speed 0001: Generation 1 communication rate (1.5 Gb/s) 0010: Generation 2 communication rate (3 Gb/s) Others: Reserved This field indicates the interface device detection and PHY state. 0000: No device detected and PHY communication not established 0001: Device presence detected, but PHY communication not established 0010: Device presence detected and PHY communication established 0110: PHY in off-line mode as a result of the interface being disabled or running in a BIST loopback mode Others: Reserved, no action 11 3 10 IPM 2 DET Default 0x0000 0 0x0 1 0 9 8 31 30 29 28 RSVD0 19 18 17 16 27 26 25 24 7:4 SPD R 0x0 3:0 DET R 0x0 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 17 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x01 PSCR[01] Name SError 23 15 7 Bit 31:16 Label DIAG R/W R/W 22 14 6 21 13 5 20 DIAG 12 ERR 4 ERR Description This field contains bits as defined in Table 4. Writing a 1 to the register bit clears the B, C, F, N, H, W, and X bits. Writing a 1 to the corresponding bits in the Port Interrupt Status register also clears the F, N, W, and X bits. The B, C, and H bits operate independently of the corresponding Error Counter registers. If the error counters are used, these bits should be ignored. This field is not implemented; all bits are always zero. Default 0x0000 3 2 1 0 11 10 9 8 31 30 29 28 DIAG 19 18 17 16 27 26 25 24 15:0 ERR R/W 0x0000 Table 4: SError Bit Definitions Bit B C D F I N H R S T W Definition 10b to 8b decode error CRC error Disparity error Unrecognized FIS type PHY internal error PHYRDY change Handshake error Reserved Link sequence error Transport state transition error ComWake Description Latched decode error or disparity error from the Serial ATA PHY Latched CRC error from the Serial ATA PHY N/A; always 0. This error condition is combined with the decode error and reported as B errors. Latched unrecognized FIS error from the Serial ATA link N/A; always 0 Indicates a change in the status of the Serial ATA PHY Latched handshake error from the Serial ATA PHY Always 0 N/A; always 0 N/A; always 0 Latched ComWake status from the Serial ATA PHY (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 18 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Addr 0x02 PSCR[02] Name SControl 23 15 7 Bit 31:20 19:16 15:12 Label RSVDRW PMP SPM R/W R/W R/W R/W 22 21 RSVDRW 14 13 SPM 6 5 SPD 31 30 29 28 27 26 18 PMP 12 4 Description This bit field is reserved and returns the value written to it. This field identifies the currently selected Port Multiplier port for accessing the SActive register and some bit fields of the Diagnostic registers. This field selects a power management state. A non-zero value written to this field causes initiation of the select power management state. This field self-resets to 0 as soon as action begins to initiate the power management state transition. 0000: No power management transition requested 0001: Transition to the partial power management state initiated 0010: Transition to the slumber power management state initiated 0100: Transition from a power management state initiated (ComWake asserted) Others: Reserved This field identifies the interface power management states that may be invoked via Serial ATA interface power management capabilities. 0000: No interface power management restrictions (partial and slumber modes enabled) 0001: Transitions to the partial power management state are disabled 0010: Transitions to the slumber power management state are disabled 0011: Transitions to both the partial and slumber power management states are disabled Others: Reserved This field identifies the highest allowed communication speed the interface is allowed to negotiate. 0000: No restrictions (default value) 0001: Limit to Generation 1 (1.5 Gb/s) 0010: Limit to Generation 2 (3.0 Gb/s) Others: Reserved This field controls host adapter device detection and interface initialization. 0000: No action 0001: COMRESET is periodically generated until another value is written to the field 0100: No action Others: Reserved; no action 31 23 15 7 Bit 31:00 Label RSVD0 R/W R 30 22 14 6 29 21 13 5 28 RSVD0 20 RSVD0 12 RSVD0 4 RSVD0 Description This bit fields are reserved and return a zero value. Default 0x0000 0000 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 11 3 10 IPM 2 DET Default 0x000 0x0 0x0 1 0 9 8 25 17 24 16 RSVDRW 20 19 11:8 IPM R/W 0x0 7:4 SPD R/W 0x0 3:0 DET R/W 0x0 Addr 0x03 - 0x0F PSCR[03-15] Name Reserved 24 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 19 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Device Initialization Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM EEPROM Specifications The port multiplier requires an external 64 kByte (or two 64 kByte EEPROMs for double buffering) serial EEPROM (400 KHz) memory device. When double buffering is used (for fail over purposes) the primary EEPROM address must be set to "000" and the secondary EEPROM address must be set to "001". When powered-up, the port multiplier verifies the checksum in the primary EEPROM before loading the firmware. If the checksum does not match, the port multiplier loads the firmware from the secondary EEPROM. The firmware contained in the EEPROM is shown below: Address 0x0000 - 0xFFED 0xFFEC - 0xFFF3 0xFFF4 - 0xFFF7 0xFFF8 - 0xFFFB 0xFFFC - 0xFFFF Code to configure the SiI 3726 System Information, may contain the Serial Number, must be an ASCII string (null terminated) Vendor ID and Chip ID 0x10953726 Firmware Revision Signature / CheckSum Contents The sequence of events is as follows: 1. System power-up 2. Code transfer from the EEPROM (I2C) to the SiI 3726 SATA Port Multiplier (boot) 3. The port multiplier starts operating under software control (normal operation) EEPROM Read/Write Operations The timing diagram for read or write operations is shown in Figure 3. The high-level timing for a random read or write is shown in Figure 4. The high-level timing for a block transfer is shown in Figure 5. EPR_SC EPR_SD Start Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ack Stop Figure 3: I2C Transfer Timing S Control Byte Address Hi Address Lo S Control Byte EPR_SC EPR_SD EPR_SD S 1 0 1 0 0 0 0 0 A A7 A6 A5 A4 A3 A2 A1 A0 A A7 A6 A5 A4 A3 A2 A1 A0 A S 1 0 1 0 0 0 0 1 A Random Read Command S 1 0 1 0 0 0 0 0 A A7 A6 A5 A4 A3 A2 A1 A0 A A7 A6 A5 A4 A3 A2 A1 A0 A Random Write Command (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 20 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Figure 4: I2C Random Read and Write Timing (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 21 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. EPR_SC Data LLLL Data LLLH Data LLHL Data LLHH 1 ST DW (R/W) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data LHLL Data LHLH Data LHHL Data LHHH 2 3 ND DW(R/W) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data HLLL RD Data HLLH Data HLHL Data HLHH DW (R/W) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A Data HHLL Data HHLH Data HHHL Data HHHH 4 4 TH DW (Read) DW (Write) D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N/A P Data HHLL TH Data HHLH Data HHHL Data HHHH D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P Figure 5: I2C Block Transfer System Reset System reset (pin A10) must be low whenever the voltage is in or out of operation range and remain for 100 ms after both 1.8V and 3.3V are stable. An example circuit is shown in Figure 6. 3.3 V VCC Reset System Reset 0.1uF GND ST Micro STM 809SWX6F or Fairchild FM809SS3X 100K GND Figure 6: Power-Up Reset Circuit (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 22 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Electrical Characteristics Specifications are for commercial temperature ranges, 0C to +70C, unless otherwise specified. Absolute Maximum Ratings Table 5 specifies the absolute maximum ratings for the device. Table 5: Absolute Maximum Ratings Symbol VDDO VDDA, VDDI VIN VCLKI_IN IOUT JA I/O supply voltage Core supply voltage Input voltage for 3.3V I/O Input voltage for CLKI DC output current Thermal resistance Parameter Rating 4.0 2.15 -0.3 ~ VDDO+0.3 -0.3 ~ VDDA+0.3 16 17.6 Unit V V V V mA C/W DC Specifications Table 6 specifies the DC specifications of the device. Table 6: DC Specifications Type Limits Symbol VDDA VDDI VDDO IDD1.8V VIH VIL IIH IIL IILOD VOH VOL IOZ Parameter Analog supply voltage Digital supply voltage I/O supply voltage 1.8V supply voltage Input high voltage Input low voltage Input high current Input low current Open drain sink current Output high voltage Output low voltage 3-State Leakage Current Condition Minimum 1.71 1.71 3.0 2.0 VIN = VDD VIN = VSS -10 -10 2.4 0.4 -10 0.8 10 10 12 Typical 1.8 1.8 3.3 8001 Maximum 1.89 1.89 3.6 13002 Units V V V mA V V A A mA V V A Notes: Note 1: Attached to the 3 G host and all device ports attached to 1.5 G devices. Note 2: Attached to 3 G host and devices. Notes 1 and 2: 3.3V power consumption depends upon the LED, JTAG, I2C and enclosure management status. If all are disabled, 3.3V power consumption will be uA. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 23 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Interface DC Specifications Table 7 shows the SATA interface DC specifications. Table 7: SATA Interface DC Specifications Type Limits Symbol VDOUT_00 Parameter TX+/- Differential peak-topeak voltage swing Condition 50 Termination PHY Configuration Setting = 000b for host port and 00b for device ports Minimum 500 Typical 550 Maximum 650 Units mV VDIN VSQ VDOH VACCM VDIH ZDIN ZDOUT ZSIN ZSOUT Rx+/Rx- Differential peakto-peak input sensitivity Rx+/Rx- OOB signal detection threshold Tx+/Tx- Differential output common-mode voltage Tx AC common-mode voltage Rx+/Rx- Differential input common-mode voltage Tx Pair differential impedance Rx Pair differential impedance Tx Single-ended impedance Rx Single-ended impedance 240 50 Must be AC coupled VDD-375 125 VDD-250 240 VDD-125 50 Must be AC coupled RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% RREF1 = 1 kOhms 1% RREF2 = 4.99 kOhms 1% -50 85 85 40 40 0 100 100 50 115 115 mV mV mV mV mV Maximum Amplitude Minimum Amplitude Peak-to peak Total Jitter Figure 7: Eye Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 24 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. CLKI SerDes Input Reference Clock Requirements Table 8 shows the input reference clock requirements. Table 8: CLK1 SerDes Reference Clock Input Requirements Type Limits Symbol TCLKI_FREQ VCLKI_IH VCLKI_IL TCLKI_J TCLKI_ RISE_FALL TCLKI_ RC_DUTY Parameter Nominal frequency Input high voltage Input Low Voltage CLKI frequency tolerance Rise and fall times at CLKI CLKI duty cycle Condition RREF1: 1Kohms 1% RREF2: 4.99Kohms 1% 25 MHz reference, 20% - 80% 20% - 80% 40 -50 0.7 x VDDA 0.3 x VDDA +50 4 60 Minimum Typical 25 Maximum Units MHz V V ppm ns % SATA Interface Timing Specifications Table 9 shows the SATA interface timing specifications. Table 9: SATA Interface Timing Specifications Type Limits Symbol TTX_RISE_FALL TTX_DC_FREQ TTX_AC_RREQ TTX_SKEW Parameter Transmitter rise and fall time Tx DC Clock frequency skew Tx AC Clock frequency skew Tx Differential skew SerDes Ref_Clk = SSC AC Modulation Condition 20%-80% at Gen1 20%-80% at Gen2 Minimum 85 67 -350 -5000 Typical Maximum 273 136 +350 +0 15 Units ps ppm ppm ps (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 25 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. SATA Interface Transmitter Output Jitter Characteristics Table 10 and Table 11 show the SATA output jitter characteristics. Table 10: SATA Interface Transmitter Output Jitter Characteristics (1.5 G) Type Limits Symbol TJ5UI_1.5 G Parameter Total Jitter, DataData 5UI Deterministic Jitter, Data-Data 5UI Total Jitter, DataData 250UI Deterministic Jitter, Data-Data 250UI Condition Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Measured at Tx output pins peak to peak phase variation Random data pattern Minimum Typical 58 Maximum Units ps DJ5UI_1.5 G 15 ps TJ250UI_1.5 G 55 ps DJ250UI_1.5 G 15 ps Table 11: SATA Interface Transmitter Output Jitter Characteristics (3.0 G) Type Limits Symbol TJfBAUD/ 10_3.0G Parameter Total Jitter, fC3dB=fBAUD/10 Deterministic Jitter, fC3dB=fBAUD/10 Total Jitter, fC3dB=fBAUD/50 0 Deterministic Jitter, fC3dB=fBAUD/50 0 Total Jitter, fC3dB=fBAUD/16 67 Deterministic Jitter, fC3dB=fBAUD/16 67 Condition Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Measured at SATA Compliance Point Random data pattern Load = LL Laboratory Load Minimum Typical 63 Maximum Units ps DJfBAUD/ 10_3.0G 16 ps TJfBAUD/ 500_3.0G 63 ps DJfBAUD/ 500_3.0G 21 ps TJfBAUD/ 1667_3.0G 86 ps DJfBAUD/ 1667_3.0G 20 ps (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 26 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Pin Descriptions SiI 3726 SATA Port Multiplier Pin-out Table 12 and Table 13 list the SiI 3726 SATA Port Multiplier pin numbers, names, types, and descriptions. Table 12 is sorted by pin name, and Table 13 is sorted by pin number. Note that NC (No Connect pins) must not be connected to any circuitry on the PCB. Table 12: SII3726 Pin List (Sorted by Pin Name) Pin Number Y11 D16 C15 C11 C10 C9 C8 C7 C6 B5 B6 Internal Resistor Pin Name CONT_DIS DAIO0 DAIO1 DBIO0 DBIO1 DCIO0 DCIO1 DDIO0 DDIO1 DEIO0 DEIO1 Type Input Input Input Input Input Input Input Input Input Input Input Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Description CONT disable in OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Device0 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device0 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device1 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device1 interface optimization input bit. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device3 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization. on page 9. Device3 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device4 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device4 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Enclosure management ID input bit 0. This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management ID input bit 1.This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management ID input bit 2 This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial clock. This pin is used to send/receive serial clock to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. Enclosure management serial data. This pin is used to send/receive serial data to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. A11 EM_ID0 Input Pull-Down (60 k) B11 EM_ID1 Input Pull-Down (60 k) B10 EM_ID2 Input Pull-Down (60 k) A12 EM_SC I/O Pull-Up (70 k) 4 mA Pull-Up (70 k) 4 mA B12 EM_SD I/O (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 27 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. EEPROM serial clock. This pin is used to send serial clock to EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. EEPROM serial data. This pin is used to send/receive serial data to/from EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. GPI signal bit 31 GPO signal bit 31 GPO signal bit 30 GPO signal bit 21 GPO signal bit 20 GPO signal bit 19 GPO signal bit 18 GPO signal bit 17 GPO signal bit 16 GPO signal bit 15 GPO signal bit 14 GPO signal bit 13 GPO signal bit 12 GPO signal bit 11 GPO signal bit 10 GPO signal bit 1 GPO signal bit 0 Host interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 2. For details, see High Speed Serial Interface Optimization on page 9. LED device port0 [0]. This pin indicates the status of device port0 together with LED_A1 pin. For details, see LED Modes on page 8. LED device port0 [1]. This pin indicates the status of device port0 together with LED_A0 pin. For details, see LED Modes on page 8. LED device port1 [0]. This pin indicates the status of device port1 together with the LED_B1 pin. For details, see LED Modes on page 8. LED device port1 [1]. This pin indicates the status of device port1 together with the LED_B0 pin. For details, see LED Modes on page 8. LED device port2 [0]. This pin indicates the status of device port2 together with the LED_C1 pin. For details, see LED Modes on page 8. LED device port2 [1]. This pin indicates the status of device port2 together with the LED_C0 pin. For details, see LED Modes on page 8. A9 EPR_SC I/O Pull-Up (70 k) 4 mA B9 EPR_SD I/O Pull-Up (70 k) 4 mA B3 W4 Y4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 W17 Y17 C14 C13 C12 Y16 GPI 31 GPO 31 GPO 30 GPO 21 GPO 20 GPO 19 GPO 18 GPO 17 GPO 16 GPO 15 GPO 14 GPO 13 GPO 12 GPO 11 GPO 10 GPO 1 GPO 0 HIO0 HIO1 HIO2 LED_A0 Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Pull-Down (60 k) 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA W16 LED_A1 Y14 LED_B0 W14 LED_B1 Y7 LED_C0 W7 LED_C1 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 28 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Y6 LED_D0 Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Input Output-Open Drain Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Down (60 k) Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA LED device port3 [0]. This pin indicates the status of device port3 together with the LED_D1 pin. For details, see LED Modes on page 8. LED device port3 [1]. This pin indicates the status of device port3 together with the LED_D0 pin. For details, see LED Modes on page 8. LED device port4 [0]. This pin indicates the status of device port4 together with the LED_E1 pin. For details, see LED Modes on page 8. LED device port4 [1]. This pin indicates the status of device port4 together with the LED_E0 pin. For details, see LED Modes on page 8. LED host port [0] This pin, together with the LED_H1 pin, indicates the status of the host port. For details, see LED Modes on page 8. LED host port [1]. This pin indicates the status of host port together with the LED_H0 pin. For details, see LED Modes on page 8. Select LED mode. For details, see LED Modes on page 8. System LED [0]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [1]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [2]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. System LED [3]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry W6 LED_D1 Y5 LED_E0 W5 LED_E1 Y15 LED_H0 W15 A3 Y13 LED_H1 LED_MODE LED_S0 W13 LED_S1 Output-Open Drain Y8 LED_S2 Output-Open Drain W8 A13 A14 A15 A16 A17 A4 B13 B14 B15 B16 B17 B4 H18 H19 J18 K16 M1 M3 M5 N1 N2 LED_S3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Output-Open Drain - (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 29 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. N3 W10 W11 W9 Y10 Y9 Y12 J20 H20 J19 M2 A10 U19 F19 D2 H2 R2 L20 U20 F20 D1 H1 R1 L19 A8 B8 A7 B7 A6 W12 R20 D20 F1 NC NC NC NC NC NC OOB_BP PCLKI1 PCLKO1 RREF1 RREF2 RST_N RXNDA RXNDB RXNDC RXNDD RXNDE RXNH RXPDA RXPDB RXPDC RXPDD RXPDE RXPH TCK TDI TDO TMS TRSTN TX_GEN TXNDA TXNDB TXNDC Input Input Output Input Input Input-Schmitt Trigger Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Output Output Output Pull-Down (60 k) Pull-Up (70 k) Pull-Up (70 k) Pull-Up (70 k) Pull-Up (70 k) Pull-Down (60 k) Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry OOB Bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. Crystal oscillator Input or external clock input (25 MHz crystal) Crystal oscillator output (25 MHz crystal) External reference resistor input, 1 k 1% resistor needs to be connected. External Reference Resistor Input, 4.99 k 1% resistor needs to be connected System Reset. This pin is used to reset the SiI 3726. Serial device port0 differential receiver - input. Must be AC coupled. Serial device port1 differential receiver - input. Must be AC coupled.. Serial device port2 differential receiver - input. Must be AC coupled.. Serial device port3 differential receiver - input. Must be AC coupled.. Serial device port4 differential receiver - input. Must be AC coupled. Serial host port differential receiver - input. Must be AC coupled. Serial device port0 differential receiver + input. Must be AC coupled. Serial device port1 differential receiver + input. Must be AC coupled. Serial device port2 differential receiver + input. Must be AC coupled. Serial device port3 differential receiver + input. Must be AC coupled. Serial device port4 differential receiver + input. Must be AC coupled. Serial HOST port differential receiver + input. Must be AC coupled. JTAG clock JTAG data Input JTAG data output JTAG mode select JTAG reset. This pin must be tied to ground if the JTAG function is not used. Tx generation rate in OOB Bypass mode. Leave NC for normal operation mode. For details, see Tx Eye Measurement on page 9. Serial device port0 differential transmitter - output. Must be AC coupled. Serial device port1 differential transmitter - output. Must be AC coupled. Serial device port2 differential transmitter - output. Must be AC coupled. (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 30 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. K1 U1 N19 R19 D19 F2 K2 U2 N20 TXNDD TXNDE TXNH TXPDA TXPDB TXPDC TXPDD TXPDE TXPH Output Output Output Output Output Output Output Output Output Serial device port3 differential transmitter - output. Must be AC coupled. Serial device port4 differential transmitter - output. Must be AC coupled. Serial HOST port differential transmitter - output. Must be AC coupled. Serial device port0 differential transmitter + output. Must be AC coupled. Serial device port1 differential transmitter + output. Must be AC coupled. Serial device port2 differential transmitter + output. Must be AC coupled. Serial device port3 differential transmitter + output. Must be AC coupled. Serial device port4 differential transmitter + output. Must be AC coupled. Serial host port differential transmitter + output. Must be AC coupled. Table 13: SII3726 Pin List (Sorted by Pin Number) Pin Number A3 A4 A5 A6 A7 A8 Internal Resistor Pin Name LED_MODE NC GPI 26 TRSTN TDO TCK Type Input Input Input Output Input Pull-Down (60 k) Pull-Down (60 k) Pull-Up (70 k) Pull-Up (70 k) Description Select LED mode. For details, see LED Modes on page 8. Do not connect to any circuitry GPI signal bit 26 JTAG reset. This pin must be tied to ground if the JTAG function is not used. JTAG data output JTAG clock EEPROM serial clock. This pin is used to send serial clock to EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. A10 RST_N InputSchmitt Trigger Input System Reset. This pin is used to reset SiI 3726 A9 EPR_SC I/O Pull-Up (70 k) 4 mA A11 EM_ID0 Pull-Down (60 k) Enclosure management ID input bit 0. This pin is used to set the identification number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial clock. This pin is used to send/receive serial clock to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry A12 A13 A14 A15 A16 A17 EM_SC NC NC NC NC NC I/O - Pull-Up (70 k) 4 mA - (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 31 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. A18 B3 B4 B5 B6 B7 B8 GPI 0 GPI 31 NC DEIO0 DEIO1 TMS TDI Input Input Input Input Input Input Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Up (70 k) Pull-Up (70 k) GPI signal bit 0 GPI signal bit 31 Do not connect to any circuitry Device4 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device4 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. JTAG mode select JTAG data input EEPROM serial data. This pin is used to send/receive serial data to/from EEPROM having I2C interface to download firmware from EEPROM. For details, see Firmware must be downloaded into the SiI 3726 SATA Port Multiplier from a Serial EEPROM for normal operation. The serial EEPROM is connected to pin numbers A9 (Serial Clock) and B9 (Serial Data). Auto-Initialization from the EEPROM on page 20. B10 EM_ID2 Input Pull-Down (60 k) Enclosure management ID input bit 2. This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management ID input bit 1. This pin is used to This pin is used to set the Identification Number together with other EM_ID pins for SEMB. For details, see Storage Enclosure Support on page 11. Enclosure management serial data. This pin is used to send/receive serial data to/from Enclosure processor, and complies with I2C Bus Specification. For details, see Storage Enclosure Support on page 11. Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry GPI signal Bit 1 GPI signal Bit 28 Device3 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device3 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Device2 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. Device1 interface optimization input bit. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 2. For details, see High Speed Serial Interface Optimization on page 9. Host interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9.. B9 EPR_SD I/O Pull-Up (70 k) 4 mA B11 EM_ID1 Input Pull-Down (60 k) B12 B13 B14 B15 B16 B17 B18 C5 C6 C7 C8 C9 C10 C11 C12 C13 EM_SD NC NC NC NC NC GPI 1 GPI 28 DDIO1 DDIO0 DCIO1 DCIO0 DBIO1 DBIO0 HIO2 HIO1 I/O Input Input Input Input Input Input Input Input Input Input Pull-Up (70 k) 4 mA Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 32 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. C14 C15 C16 D1 D2 D5 D16 D19 D20 F1 F2 F19 F20 H1 H2 H18 H19 H20 J18 J19 J20 K1 K2 K16 L19 L20 M1 M2 M3 M5 N1 HIO0 DAIO1 GPI 13 RXPDC RXNDC GPI 29 DAIO0 TXPDB TXNDB TXNDC TXPDC RXNDB RXPDB RXPDD RXNDD NC NC PCLKO1 NC RREF1 PCLKI1 TXNDD TXPDD NC RXPH RXNH NC RREF2 NC NC NC Input Input Input Input Input Input Input Output Output Output Output Input Input Input Input Output Input Input Output Output Input Input Input Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Pull-Down (60 k) Host interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9.. Device0 interface optimization input bit 1. For details, see High Speed Serial Interface Optimization on page 9. GPI signal Bit 13 Serial device port2 differential receiver + input. Must be AC coupled. Serial device port2 differential receiver + input. Must be AC coupled. GPI signal Bit 29 Device0 interface optimization input bit 0. For details, see High Speed Serial Interface Optimization on page 9. Serial device port1differential transmitter + output. Must be AC coupled. Serial device port1 differential transmitter - output. Must be AC coupled. Serial device port2 differential transmitter - output. Must be AC coupled. Serial device port2 differential transmitter + output. Must be AC coupled. Serial device port1 differential receiver - input. Must be AC coupled. Serial device port1 differential receiver + input. Must be AC coupled. Serial device port3 differential receiver + input. Must be AC coupled. Serial device port3 differential receiver + input. Must be AC coupled. Do not connect to any circuitry Do not connect to any circuitry Crystal oscillator output (25 MHz crystal) Do not connect to any circuitry External reference resistor input. 1 k 1% resistor needs to be connected. Crystal oscillator Input or external clock input (25 MHz crystal) Serial device port3 differential transmitter - output. Must be AC coupled. Serial device port3 differential transmitter - output. Must be AC coupled. Do not connect to any circuitry Serial host port differential receiver + input. Must be AC coupled. Serial host port differential receiver + input. Must be AC coupled. Do not connect to any circuitry External reference resistor input. 4.99 k 1% resistor needs to be connected Do not connect to any circuitry Do not connect to any circuitry Do not connect to any circuitry (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 33 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. N2 N3 N19 N20 R1 R2 R19 R20 U1 U2 U19 U20 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 W4 W5 NC NC TXNH TXPH RXPDE RXNDE TXPDA TXNDA TXNDE TXPDE RXNDA RXPDA GPO 21 GPO 20 GPO 19 GPO 18 GPO 17 GPO 16 GPO 15 GPO 14 GPO 13 GPO 12 GPO 11 GPO 10 GPO 31 LED_E1 Output Output Input Input Output Output Output Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Do not connect to any circuitry Do not connect to any circuitry Serial host port differential transmitter - output. Must be AC coupled. Serial host port differential transmitter + output. Must be AC coupled. Serial device port4 differential receiver + input. Must be AC coupled. Serial device port4 differential receiver - input. Must be AC coupled. Serial device port0 differential transmitter + output. Must be AC coupled. Serial device port0 differential transmitter - output. Must be AC coupled. Serial device port4 differential transmitter - output. Must be AC coupled. Serial device port4 differential transmitter + output. Must be AC coupled. Serial device port0 differential receiver - input. Must be AC coupled. Serial device port0 differential receiver + input. Must be AC coupled. GPO signal bit 21 GPO signal bit 20 GPO signal bit 19 GPO signal bit 18 GPO signal bit 17 GPO signal bit 16 GPO signal bit 15 GPO signal bit 14 GPO signal bit 13 GPO signal bit 12 GPO signal bit 11 GPO signal bit 10 GPO signal bit 31 LED device port4 [1]. This pin indicates the status of device port4 together with LED_E0 pin. For details, see LED Modes on page 8. LED device port3 [1]. This pin indicates the status of device port3 together with LED_D0 pin. For details, see LED Modes on page 8. LED device port2 [1]. This pin indicates the status of device port2 together with LED_C0 pin. For details, see LED Modes on page 8. System LED [3]. This pin indicates the status of firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Do not connect to any circuitry Do not connect to any circuitry W6 LED_D1 W7 LED_C1 W8 W9 W10 LED_S3 NC NC (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 34 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. W11 W12 NC TX_GEN Pull-Down (60 k) Do not connect to any circuitry Tx generation rate in OOB Bypass mode. Leave NC for normal operation mode. For details, see Tx Eye Measurement on page 9. System LED [1]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. LED device port1 [1]. This pin indicates the status of device port1 together with LED_B0 pin. For details, see LED Modes on page 8. LED host port [1]. This pin indicates the status of host port together with LED_H0 pin. For details, see LED Modes on page 8. LED device port0 [1]. This pin indicates the status of device port0 together with LED_A0 pin. For details, see LED Modes on page 8. GPO signal bit 1 GPO signal bit 30 LED device port4 [0]. This pin indicates the status of device port4 together with LED_E1 pin. For details, see LED Modes on page 8. LED device port3 [0]. This pin indicates the status of device port3 together with LED_D1 pin. For details, see LED Modes on page 8. LED device port2 [0]. This pin indicates the status of device port #2 together with LED_C1 pin. For details, see LED Modes on page 8. System LED [2]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. Do not connect to any circuitry Do not connect to any circuitry CONT disable in OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. OOB bypass mode. Leave NC for normal operation. For details, see Tx Eye Measurement on page 9. System LED [0]. This pin indicates the status of the firmware loading during boot-up, and the system after then together with other LED_S pins. For details, see LED Modes on page 8. LED device port1 [0]. This pin indicates the status of device port1 together with LED_B1 pin. For details, see LED Modes on page 8. LED host port [0]. This pin indicates the status of HOST port together with LED_H1 pin. For details, see LED Modes on page 8. LED device port0 [0]. This pin indicates the status of device port0 together with LED_A1 pin. For details, see LED Modes on page 8. GPO signal bit 0 W13 LED_S1 Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output Output Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Input Input Output-Open Drain Output-Open Drain Output-Open Drain Output-Open Drain Output Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA 8 mA 8 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Down (60 k) Pull-Down (60 k) Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA Pull-Up (70 k) 12 mA 8 mA W14 LED_B1 W15 LED_H1 W16 W17 Y4 Y5 LED_A1 GPO 1 GPO 30 LED_E0 Y6 LED_D0 Y7 LED_C0 Y8 Y9 Y10 Y11 Y12 LED_S2 NC NC CONT_DIS OOB_BP Y13 LED_S0 Y14 LED_B0 Y15 LED_H0 Y16 Y17 LED_A0 GPO 0 Table 14: Power Supply Pin List (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 35 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Pin Number A1, B2, C1, C3, D4, E1, E3, F4, G1, G3, H5 H4, J1, J3, K4, K5, L1, L3 N4, N5, P1, P3 P5, R4, T1, T3, U4, V1 V3, W2, Y1, Y3 D6, D10, D11, D15, E5, E6, E10, E11, E15, E16, F5, T5, T6, T7, T14, T15, T16, U5, U6, U7, U14, U15, U16 D7, D8, D9, D12, D13, D14, E7, E8, E9, E12, E13, E14, T8, T9, T10, T11, T12, T13, U8, U9, U10, U11, U12, U13 P16, P18, P20, R17, T18, T20, U17, V18, V20, W19, Y18, Y20 K18, K20, L17, M16, M18, M20, N17 G18, G20, H17, J16 D17, E18, E20, F17, G16 A20, B19, C18, C20 Pin Name VDD RX3 VDD TX3 VDD P2 VDD RX4 VDD TX4 3V3DDO Type Power Description VDD (1.8V) for SATA PHY Receiver3 VDD (1.8V) for SATA PHY Transmitter3 VDD (1.8V) for SATA PHY PLL2 VDD (1.8V) for SATA PHY Receiver4 VDD (1.8V) for SATA PHY Transmitter4 VDD I/O (3.3V) Power Power Power Power Power Power Power Power Power Power Power VDDD VDD (1.8V) VDD RX1 VDD TX1 VDD P1 VDD RX2 VDD TX2 VDD (1.8V) for SATA PHY Receiver1 VDD (1.8V) for SATA PHY Transmitter1 VDD (1.8V) for SATA PHY PLL1 VDD (1.8V) for SATA PHY Receiver2 VDD (1.8V) for SATA PHY Transmitter2 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 36 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Package Pin Descriptions Pin Descriptions Figure 8 shows the Pin-Diagram for the 21 mm x 21 mm BGA with a 20 x 20 array of Balls. 1 A B C D E F G H J K L M N P R T U V W Y VDD P2 VDD RX3 2 VSS VDD RX3 3 4 5 6 7 TDO 8 TCK TDI DCI O1 VDD D VDD D 9 EPR SC EPR SD DCI O0 VDD D VDD D 10 11 12 13 14 15 16 17 18 19 20 RST N EMID EM S NC [0] C LED NC GPI TRS MODE [26] TN NC NC NC NC NC NC NC GPI [0] GPI [1] VDD TX2 VSS VDD TX2 VDD TX2 A B C D E F G H J K L M N P R T U V W Y VSS VDD RX3 GPI NC DEIO DEIO TMS [31] 0 1 VDD RX3 EMID EMID EM S [2] [1] D DBI O1 3V3 DDO 3V3 DDO NC HI O1 VDD D VDD D NC HI O0 VDD D VDD D VSS VDD TX2 VSS DC RxN VSS VDD RX3 GPI DDI [28] O1 GPI [29] 3V3 DDO 3V3 DDO 3V3 DDO 3V3 DDO DDI O0 VDD D VDD D DBI O0 3V3 DDO 3V3 DDO HI O2 VDD D VDD D DAI GPI O1 [13] 3V3 DDO 3V3 DDO VSS VDD RX2 VSS DB TxP DC RxP VDD RX3 VSS VDD RX3 DAI O0 3V3 DDO VSS VDD RX2 DB TxN VDD RX2 VSS DC TxP VSS VDD RX3 VSS VDD RX2 VSS DB RxN DC TxN VDD RX3 VSS VDD RX3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD RX2 VSS VDD P1 DB RxP VDD P1 VSS DD RxN VSS VDD TX3 VSS VDD RX3 VSS VDD P1 VSS NC PR EF1 DD RxP VDD TX3 VSS VDD TX3 VSS VDD P1 NC NC VDD TX1 PCL KO1 PCL KI1 VDD TX1 VSS DD TxP VSS VDD TX3 VSS VDD TX3 VSS VSS VDD TX1 DD TxN VDD TX3 VSS VDD TX3 NC VSS H RxP VSS PR EF2 VSS VSS VDD P2 VSS NC VDD P2 VDD RX4 VSS VDD TX1 VSS VDD TX1 H RxN VDD TX1 NC NC NC NC VDD P2 VSS VDD TX1 VSS H TxN NC VSS VDD RX1 VSS VDD RX1 H TxP VDD RX1 VSS DE RxN VSS VDD RX4 VSS VDD RX1 VSS DA TxP DE RxP VDD RX4 VSS VDD RX4 VSS 3V3 DDO 3V3 DDO 3V3 DDO 3V3 DDO 3V3 DDO 3V3 DDO VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D VDD D 3V3 DDO 3V3 DDO 3V3 DDO 3V3 DDO VSS 3V3 DDO 3V3 DDO VSS VDD RX1 DA TxN VDD RX1 VSS DE TxP VSS VDD RX4 VSS VDD RX1 VSS DA RxN DE TxN VDD RX4 VSS VDD TX4 VSS VDD RX1 DA RxP VDD RX1 VSS VDD TX4 VSS GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO GPO [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] VSS GPO [1] GPO [0] VSS VDD RX1 VSS VDD TX4 VSS VDD TX4 GPO LED LED LED LED NC [31] E[1] D[1] C[1] S[3] GPO LED LED LED LED NC [30] E[0] D[0] C[0] S[2] NC NC TX LED LED LED LED GEN S[1] B[1] H[1] A[1] VSS VDD RX1 VSS VDD RX1 VSS NC CONT OOB LED LED LED LED _DIS _BP S[0] B[0] H[0] A[0] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 8: Sil3726 Pinout Diagram (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 37 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Package Information Dimensions Figure 9 shows the dimensions of the 364-Ball HSBGA package. 1.00 0.36 0.50 0.85 Figure 9: 364 Ball HSBGA Package Dimensions (in Millimeters) (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 38 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Part Ordering Numbers: * * SII3726CB (364-pin BGA, standard package) shown in Figure 10. SII3726CBHU (364-pin BGA, green package) shown in Figure 11. Pin 1 Designator Location Logo Trademark SII3726CB LLLLLL.LLLL YYWW XXXXXXX SiI Part No. Lot No. (= Job No.) Date Code Trace No. Figure 10: Marking Specification - SII3726CB Pin 1 Designator Location Logo Trademark SII3726CBHU LLLLLL.LLLL YYWW XXXXXXX SiI Part No. Lot No. (= Job No.) Date Code Trace No. Figure 11: Marking Specification - SII3726CBHU (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 39 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. References For more details about Serial ATA technology, refer to the following industry specifications: * * * * * Serial ATA /High Speed AT Attachment Specification, Revision 1.0a Serial ATA II: Extensions to Serial ATA 1.0a, Revision 1.2 Serial ATA II: Port Multiplier, Revision 1.1 and Revision 1.2 Release Candidate Serial ATA II: Electrical Specification, Revision 1.0 Serial ATA II: Cables and Connectors, Volumes 1 and 2 (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 40 SII3726 SATA Port Multiplier Data Sheet Silicon Image, Inc. Disclaimers These materials are provided on an "AS IS" basis. Silicon Image, Inc. and its affiliates disclaim all representations and warranties (express, implied, statutory or otherwise), including but not limited to: (i) all implied warranties of merchantability, fitness for a particular purpose, and/or non-infringement of third party rights; (ii) all warranties arising out of course-of-dealing, usage, and/or trade; and (iii) all warranties that the information or results provided in, or that may be obtained from use of, the materials are accurate, reliable, complete, up-to-date, or produce specific outcomes. Silicon Image, Inc. and its affiliates assume no liability or responsibility for any errors or omissions in these materials, makes no commitment or warranty to correct any such errors or omissions or update or keep current the information contained in these materials, and expressly disclaims all direct, indirect, special, incidental, consequential, reliance and punitive damages, including WITHOUT LIMITATION any loss of profits arising out of your access to, use or interpretation of, or actions taken or not taken based on the content of these materials. Silicon Image, Inc. and its affiliates reserve the right, without notice, to periodically modify the information in these materials, and to add to, delete, and/or change any of this information. Notwithstanding the foregoing, these materials shall not, in the absence of authorization under U.S. and local law and regulations, as required, be used by or exported or re-exported to (i) any U.S. sanctioned or embargoed country, or to nationals or residents of such countries; or (ii) any person, entity, organization or other party identified on the U.S. Department of Commerce's Denied Persons or Entity List, the U.S. Department of Treasury's Specially Designated Nationals or Blocked Persons List, or the Department of State's Debarred Parties List, as published and revised from time to time; (iii) any party engaged in nuclear, chemical/biological weapons or missile proliferation activities; or (iv) any party for use in the design, development, or production of rocket systems or unmanned air vehicles. Products and Services The products and services described in these materials, and any other information, services, designs, know-how and/or products provided by Silicon Image, Inc. and/or its affiliates are provided on as "AS IS" basis, except to the extent that Silicon Image, Inc. and/or its affiliates provides an applicable written limited warranty in its standard form license agreements, standard Terms and Conditions of Sale and Service or its other applicable standard form agreements, in which case such limited warranty shall apply and shall govern in lieu of all other warranties (express, statutory, or implied). EXCEPT FOR SUCH LIMITED WARRANTY, SILICON IMAGE, INC. AND ITS AFFILIATES DISCLAIM ALL REPRESENTATIONS AND WARRANTIES (EXPRESS, IMPLIED, STATUTORY OR OTHERWISE), REGARDING THE INFORMATION, SERVICES, DESIGNS, KNOW-HOW AND PRODUCTS PROVIDED BY SILICON IMAGE, INC. AND/OR ITS AFFILIATES, INCLUDING BUT NOT LIMITED TO, ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND/OR NONINFRINGEMENT OF THIRD PARTY RIGHTS. YOU ACKNOWLEDGE AND AGREE THAT SUCH INFORMATION, SERVICES, DESIGNS, KNOW-HOW AND PRODUCTS HAVE NOT BEEN DESIGNED, TESTED, OR MANUFACTURED FOR USE OR RESALE IN SYSTEMS WHERE THE FAILURE, MALFUNCTION, OR ANY INACCURACY OF THESE ITEMS CARRIES A RISK OF DEATH OR SERIOUS BODILY INJURY, INCLUDING, BUT NOT LIMITED TO, USE IN NUCLEAR FACILITIES, AIRCRAFT NAVIGATION OR COMMUNICATION, EMERGENCY SYSTEMS, OR OTHER SYSTEMS WITH A SIMILAR DEGREE OF POTENTIAL HAZARD. NO PERSON IS AUTHORIZED TO MAKE ANY OTHER WARRANTY OR REPRESENTATION CONCERNING THE PERFORMANCE OF THE INFORMATION, PRODUCTS, KNOW-HOW, DESIGNS OR SERVICES OTHER THAN AS PROVIDED IN THESE TERMS AND CONDITIONS. 60 E. Arques Avenue Sunnyvale, CA 94085 T 408.616.4000 F 408.830.9530 www.siliconimage.com (c) 2006 Silicon Image, Inc. SiI-DS-0121-C1 41 |
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